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| Integrated Circuit Systems, Inc. ICSSSTV16857C DDR 14-Bit Registered Buffer Recommended Applications: * DDR Memory Modules * Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 * SSTL_2 compatible data registers Product Features: * Differential clock signal * Meets SSTL_2 signal data * Supports SSTL_2 class I & II specifications * Low-voltage operation - VDD = 2.3V to 2.7V * 48 pin TSSOP package Pin Configuration Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D1 D2 GND VDD D3 D4 D5 D6 D7 CLK# CLK VDD GND VREF RESET# D8 D9 D10 D11 D12 VDD GND D13 D14 Truth Table1 Inputs RESET# L H H H Notes: 1. H = High Signal Level L = Low Signal Level = Transition LOW-to-HIGH = Transition HIGH -to LOW X = Irrelevant Output level before the indicated steady state input conditions were established. Q Outputs D X or Floating H L X Q L H L Q0(2) CLK X or Floating L or H CLK# X or Floating L or H 48-Pin TSSOP & TVSOP 6.10 mm. Body, 0.50 mm. pitch = TSSOP 4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP) 2. Block Diagram CLK CLK# RESET# D1 VREF 38 39 34 48 35 R CLK D1 ICSSSTV16857C 1 Q1 To 13 Other Channels 0002F--10/25/02 ICSSSTV16857C General Description The 14-bit ICSSSTV16857C is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16857C supports low-power standby operation. A logic level "Low" at RESET# assures that all internal registers and outputs (Q) are reset to the logic "Low" state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic "Low" level during power up. In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic "Low" level quickly relative to the time to disable the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power standby state, the register will become active quickly relative to the time to enable the differential input receivers. When the data inputs are at a logic level "Low" and the clock is stable during the "Low"-to-"High" transition of RESET# until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic "Low" level. Pin Configuration PIN NUMBER 24, 23, 20, 19, 18, 15, 14, 11, 10, 7, 6, 5, 2, 1 3, 8, 13, 22, 27, 36, 46 4, 9, 12, 16, 21 25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47, 48 38 39 28, 37, 45 34 35 PIN NAME Q (14:1) GND VDDQ D (14:1) CLK CLK# VDD RESET# VREF TYPE OUTPUT PWR PWR INPUT INPUT INPUT PWR INPUT INPUT Data output Ground Output supply voltage Data input Positive clock input Negative clock input Core supply voltage Reset (active low) Input reference voltage DESCRIPTION 0002F--10/25/02 2 ICSSSTV16857C Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDD, VDDQ or GND Current/Pin . . . . . . . . . . . . -65C to +150C -0.5 to 3.6V -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 50 mA 50 mA 50 mA 100 mA Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. Package Thermal Impedance 3 . . . . . . . . . . . . . . . . 55C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions PARAMETER VDD VDDQ VREF VTT VI V IH (DC) V IH (AC) V IL (DC) V IL (DC) VIH V IL V ICR VID VIX IOH IOL TA 1 DESCRIPTION Supply Voltage I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET# Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage Cross Point Voltage of Differential Clock Pair High-Level Output Current Low-Level Output Current Operating Free-Air Temperature MIN 2.3 2.3 1.15 VREF - 0.04 0 V REF + 0.15 V REF + 0.31 TYP 2.5 2.5 1.25 VREF MAX 2.7 2.7 1.35 VREF + 0.04 VDDQ UNITS V REF - 0.15 V REF - 0.31 1.7 0.97 0.36 (VDDQ/2) - 0.2 0.7 1.53 V (VDDQ/2) + 0.2 -20 20 70 mA C 0 Guarenteed by design, not 100% tested in production. 0002F--10/25/02 3 ICSSSTV16857C Electrical Characteristics - DC TA = 0 - 70 C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL VIK VOH PARAMETERS I I = -18mA I OH = -100A I OH = -16mA I OL = 100A I OL = 16mA All Inputs V I = VDD or GND Standby (Static) RESET# = GND V I = VIH(AC) or V IL(AC), Operating (Static) RESET# = VDD RESET# = VDD, Dynamic operating V I = VIH(AC) or V IL(AC), (clock only) CLK and CLK# switching 50% duty cycle. IO = 0 RESET# = VDD, V I = VIH(AC) or V IL (AC), Dynamic Operating CLK and CLK# switching (per each data input) 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle Output High I OH = -20mA Output Low I OL = 20mA [rOH - rOL] each I O = 20mA, TA = 25 C separate bit V I = VREF 350mV Data Inputs CLK and CLK# V ICR = 1.25V, V I(PP) = 360mV CONDITIONS VDDQ 2.3V 2.3V-2.7V 2.3V 2.3V-2.7V 2.3V 2.7V V DDQ 0.2 1.95 0.2 0.35 5 0.01 52 MIN TYP MAX -1.2 UNITS V VOL II I DD A A mA 75 2.7V A/clock MHz I DDD 15 A/ clock MHz/data rOH rOL rO(D) Ci 2.3V-2.7V 2.3V-2.7V 2.5V 2.5V 7 7 13.5 13 20 20 4 pF 2.5 2.5 3.5 3.5 Notes: 1 - Guaranteed by design, not 100% tested in production. 0002F--10/25/02 4 ICSSSTV16857C Timing Requirements1 (over recommended operating free-air temperature range, unless otherwise noted) VDDQ = 2.50.2V SYMBOL PARAMETERS MIN MAX fclock Clock frequency 200 tPD tRST tSL tS Th Notes: Clock to output time Reset to output time Output slew rate Setup time, fast slew rate Setup time, slow slew rate 3 & 4 Hold time, fast slew rate 2 & 4 Hold time, slow slew rate 3 & 4 2&4 UNITS MHz ns ns V/ns ns ns ns ns 1.7 1 Data before CLK , CLK# Data after CLK , CLK# 0.4 0.5 0.4 0.5 2.5 3.5 4 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate 1V/ns. 3 - For data signal input slew rate 0.5V/ns and < 1V/ns. 4 - CLK, CLK# signals input slew rates are 1V/ns. Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1) V DD = 2.5V 0.2V From To SYMBOL UNITS MIN TYP MAX (Input) (Output) fmax 200 MHz CLK, CLK# Q 1.7 2.1 2.5 ns tPD RESET# Q 3.5 ns tphl 0002F--10/25/02 5 ICSSSTV16857C VTT RL=50 From Output Under Test Test Point CL = 30 pF (see Note 1) Load Circuit LVCMOS RESET# Input tinact IDD (see note 2) VDDQ VDDQ/2 VDDQ/2 VI(pp) 0V tact 90% IDDH 10% Voltage and Current Waveforms Inputs Active and Inactive Times tw VIH IDDL Output Timing Input tPHL VTT VTT VICR VICR tPHL VOH VOL Voltage Waveforms - Propagation Delay Times Input VREF VREF VIL LVCMOS RESET# Input VIH VDD/2 tPHL VIL Voltage Waveforms - Pulse Duration VI(pp) Timing Input tS Input VREF VICR Output VTT VIH VREF VIL Voltage Waveforms - Setup and Hold Times Voltage Waveforms - Propagation Delay Times VOL VOH th Figure 1 - Parameter Measurement Information (VDDQ = 2.5V 0.2V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDDQ or GND, and IO = 0 mA. 3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz, Zo=50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDDQ for LVCMOS input. 7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tpd 0002F--10/25/02 6 ICSSSTV16857C N c L INDEX AREA E1 E 12 D a A2 A1 A In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS -Ce b SEATING PLANE N 48 10 -0 0 3 9 D mm. MIN 12.40 MAX 12.60 MIN .488 D (inch) MAX .496 aaa C Ref erence Do c.: JEDEC Pub licat io n 9 5, M O-153 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information ICSSSTV16857CG-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0002F--10/25/02 7 ICSSSTV16857C N c L INDEX AREA E1 E 12 D A2 A1 A In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 6.40 BASIC 0.252 BASIC E E1 4.30 4.50 .169 .177 0.40 BASIC 0.016 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.08 -.003 VARIATIONS -Ce b SEATING PLANE N 48 10-0037 D mm. MIN 9.60 MAX 9.80 MIN .378 D (inch) MAX .386 aaa C R eferenc e D o c .: J ED EC P ublic atio n 95, M O-153 4.40 mm. Body, 0.40 mm. pitch TSSOP (173 mil) (16 mil) Ordering Information ICSSSTV16857CL-T Example: ICS XXXX y L - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type L = TSSOP (TVSOP) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0002F--10/25/02 8 |
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